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1 wide v in 1a synchronous buck regulator isl85410 the isl85410 is a 1a synchronous buck regulator with an input range of 3v to 36v. it provides an easy to use, high efficiency low bom count solution for a variety of applications. the isl85410 integrates both high-side and low-side nmos fet's and features a pfm mode for improved efficiency at light loads. this feature can be disabled if forced pwm mode is desired. the part switches at a default frequency of 500khz but may also be programmed usin g an external resistor from 300khz to 2mhz. the isl85410 has the ability to utilize internal or external compensation. by integrating both nmos devices and providing internal configuration options, minimal external components are required, reducing bom count and complexity of design. with the wide v in range and reduced bom the part provides an easy to implement design solution for a variety of applications while giving superior performance. it will provide a very robust design for high voltage industrial applications as well as an efficient solution for battery powered applications. the part is available in a smal l pb free 4mmx3mm dfn plastic package with an operation te mperature range of -40c to +125c related literature ?see an1905 , ?isl85410eval1z, isl85410aeval1z, isl85418eval1z wide vin 1a, 800ma synchronous buck regulator? ?see an1908 , ?isl85410demo1z, isl85418demo1z wide vin 1a, 800ma synchronous buck regulator? features ? wide input voltage range 3v to 36v ? synchronous operation for high efficiency ? no compensation required ? integrated high-side and low-side nmos devices ? selectable pfm or forced pwm mode at light loads ? internal fixed (500khz) or adjustable switching frequency 300khz to 2mhz ? continuous output current up to 1a ? internal or external soft-start ? minimal external components required ? power-good and enable functions available. applications ? industrial control ?medical devices ?portable instrumentation ? distributed power supplies ? cloud infrastructure figure 1. typical application figure 2. efficiency vs load, pfm, v out = 3.3v gnd cboot 100nf cfb r3 r2 phase ss sync boot vin pgnd fs comp fb vcc pg en cvcc 1f cvin 10f l1 22h cout 10f 1 2 3 4 5 6 9 10 11 12 internal default parameter selection cout 10f vout 50 55 60 65 70 75 80 85 90 95 100 v in = 5v v in = 15v v in = 24v v in = 12v v in = 33v output load (a) efficiency (%) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas llc 2013. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners. november 22, 2013 fn8375.2
isl85410 2 fn8375.2 november 22, 2013 table of contents typical application schematics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 thermal information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 efficiency curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 detailed description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 soft start. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 power-good . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 pwm control scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 light load operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 output voltage selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 protection features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 negative current limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 over-temperature protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 boot undervoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 application guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 simplifying the design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 operating frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 synchronization control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 output inductor selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 buck regulator output capacitor selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 loop compensation design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 layout considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 about intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 package outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
isl85410 3 fn8375.2 november 22, 2013 pin configuration isl85410 (12 ld 4x3 dfn) top view vcc en vin fb phase boot comp 1 2 3 4 5 12 11 10 9 8 pg ss fs pgnd 6 gnd 7 sync pin descriptions pin number symbol pin description 1ss the ss pin controls the soft-start ra mp time of the output. a single capacitor from the ss pin to ground determines the output ramp rate. see ?soft start? on page 14 for soft-start details. if the ss pin is tied to vcc, an internal soft-start of 2ms will be used. 2sync synchronization and light load oper ational mode selection input. connect to logic high or vcc for pwm mode. connect to logic low or ground for pfm mode. logic ground enables the ic to automatically choose pfm or pwm operation. connect to an external clock sour ce for synchronization with positive edge trigger. sync source must be higher than the programmed ic frequency. there is an internal 5m pull-down resistor to prevent an undefined logic state if sync is left floating. 3boot floating bootstrap supply pin for the power mosfet gate driver. the bootstrap capacitor provides the necessary charge to turn on the internal n-channel mo sfet. connect an external 100nf capacitor from this pin to phase. 4vin the input supply for the power stage of the regulator an d the source for the internal linear bias regulator. place a minimum of 4.7f ceramic capacitance from vin to gnd and close to the ic for decoupling. 5phase switch node output. it connects the switching fet?s with the external output inductor. 6pgnd power ground connection. connect di rectly to the system gnd plane. 7en regulator enable input. the regulator and bias ldo are held off when the pin is pulled to ground. when the voltage on this pin rises above 1v, the chip is enabled. connect this pin to vin for automatic start-up. do not connect en pin to vcc since the ldo is controlled by en voltage. 8pg open drain power-good output that is pulled to grou nd when the output voltage is below regulation limits or during the soft-start interval. there is an internal 5m internal pull-up resistor. 9vcc output of the internal 5v linear bias regulator. deco uple to pgnd with a 1f ceramic capacitor at the pin. 10 fb feedback pin for the regulator. fb is the inverting input to the voltage loop error amplifier. comp is the output of the error amplifier. the output voltage is se t by an external resistor divider connected to fb. in addition, the pwm regulator?s power-good and uvlo circ uits use fb to monitor the regulator output voltage. 11 comp comp is the output of the error amplifier. when it is tied to vcc, internal compensation is used. when only an rc network is connected from comp to gnd, exte rnal compensation is used . see ?loop compensation design? on page 17 for more details. 12 fs frequency selection pin. tie to vcc for 500khz swit ching frequency. connect a resistor to gnd for adjustable frequency from 300khz to 2mhz. epad gnd signal ground connections. connect to application boar d gnd plane with at least 5 vias. all voltage levels are measured with respect to this pin. the epad must not float.
isl85410 4 fn8375.2 november 22, 2013 typical application schematics figure 3. internal default parameter selection figure 4. user programmable parameter selection gnd cboot 100nf cfb r3 r2 phase ss sync boot vin pgnd fs comp fb vcc pg en cvcc 1f cvin 10f l1 22h cout 10f 1 2 3 4 5 6 9 10 11 12 vout gnd cboot 100nf cfb r3 r2 css ccomp rcomp rfs phase ss sync boot vin pgnd fs comp fb vcc pg en cvin 10f cvcc 1f l1 22h cout 10f 1 2 3 4 5 6 9 10 11 12 vout table 1. external component selection v out (v) l 1 (h) c out (f) r 2 (k ) r 3 (k ) c fb (pf) r fs (k ) r comp (k ) c comp (pf) 12 22 2 x 22 90.9 4.75 22 115 150 470 5 22 47 + 22 90.9 12.4 27 dnp (note 1) 100 470 3.3 22 47 + 22 90.9 20 27 dnp (note 1) 100 470 2.5 22 47 + 22 90.9 28.7 27 dnp (note 1) 100 470 1.8 12 47 + 22 90.9 45.5 27 dnp (note 1) 70 470 note: 1. connect fs to vcc
isl85410 5 fn8375.2 november 22, 2013 functional block diagram gate drive and deadtime bias ldo oscillator pfm current set fault logic 450mv/t slope compensation (pwm only) 600mv/amp current sense pwm/pfm select logic en/soft start zero current detection pwm pwm 600mv vref g m 150k 54pf internal compensation s r q q power good logic fb internal = 50s external = 230s 5m 5m pgnd phase boot vcc vin en fb fs sync comp pg gnd package paddle ss fb ordering information part number (notes 1, 2, 3) part marking temp. range (c) package (pb-free) pkg. dwg. # ISL85410FRZ 5410 -40 to +125 12 ld dfn l12.4x3 isl85410eval1z evaluation board notes: 1. add ?t? suffix for tape and reel. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ spec ial pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish , which is rohs compliant and compatible wi th both snpb and pb-free soldering opera tions). intersil pb-free products are msl classified at pb-fr ee peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jed ec j std-020. 3. for moisture sensitivity level (msl), please see device information page for isl85410 . for more information on msl please see techbrief tb363 .
isl85410 6 fn8375.2 november 22, 2013 absolute maximum rating s thermal information vin to gnd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +42v phase to gnd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to vin+0.3v (dc) phase to gnd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2v to 43v (20ns) en to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +42v boot to phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +5.5v comp, fs, pg, sync, ss, vcc to gnd . . . . . . . . . . . . . . . . . . -0.3v to +5.9v fb to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +2.95v esd rating human body model (tested per jesd22-a114) . . . . . . . . . . . . . . . . . 2kv charged device model (tested per jesd22-c101e). . . . . . . . . . . . .1.5kv latch up (tested per jesd-78a; class 2, level a) . . . . . . . . . . . . 100ma thermal resistance ja (c/w) jc (c/w) dfn package (notes 4, 5) . . . . . . . . . . . . . . 42 4.5 maximum junction temperature (plastic package) . . . . . . . . . . . .+150c maximum storage temperature range . . . . . . . . . . . . . .-65c to +150c ambient temperature range . . . . . . . . . . . . . . . . . . . . . . .-40c to +125c operating junction temperature range . . . . . . . . . . . . . .-40c to +125c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/ pbfree/pb-freereflow.asp recommended operating conditions temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40c to +125c supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3v to 36v caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ja is measured in free air with the componen t mounted on a high effective thermal conduc tivity test board with ?direct attach? fe atures. see tech brief tb379 for details. 5. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications t a = -40c to +125c, v in = 3v to 36v, unless otherwise noted. typical values are at t a = +25c. boldface limits apply over the junction temperature range, -40c to +125c parameter symbol test conditions min (note 8) typ max (note 8) units supply voltage v in voltage range v in 336 v v in quiescent supply current i q v fb = 0.7v, sync = 0v, f s = v cc 80 a v in shutdown supply current i sd en = 0v, v in =36v (note 6) 2 4 a v cc voltage v cc v in = 6v, i out = 0 to 10ma 4.5 5.1 5.7 v power-on reset v cc por threshold rising edge 2.75 2.95 v falling edge 2.35 2.6 v oscillator nominal switching frequency f s f s = v cc 430 500 570 khz resistor from f s to gnd = 340k 240 300 360 khz resistor from f s to gnd = 32.4k 2000 khz minimum off-time t off v in = 3v 150 ns minimum on-time t on (note 9) 90 ns f s voltage v fs f s = 100k 0.39 0.4 0.41 v synchronization frequency sync 300 2000 khz sync pulse width 100 ns error amplifier error amplifier transconductance gain gm external compensation 165 230 295 a/v internal compensation 50 a/v fb leakage current v fb = 0.6v 1 150 na current sense amplifier gain r t 0.46 0.5 0.54 v/a fb voltage t a = -40c to +85c 0.590 0.599 0.606 v t a = -40c to +125c 0.590 0.599 0.607 v
isl85410 7 fn8375.2 november 22, 2013 power-good lower pg threshold - vfb rising 90 94 % lower pg threshold - vfb falling 82.5 86 % upper pg threshold - vfb rising 116.5 120 % upper pg threshold - vfb falling 107 112 % pg propagation delay percentage of the soft-start time 10 % pg low voltage i sink = 3ma, en = v cc , v fb = 0v 0.05 0.3 v tracking and soft-start soft-start charging current i ss 4.2 5.5 6.5 a internal soft-start ramp time en/ss = v cc 1.5 2.4 3.4 ms fault protection thermal shutdown temperature t sd rising threshold 150 c t hys hysteresis 20 c current limit blanking time t ocon 17 clock pulses overcurrent and auto restart period t ocoff 8 ss cycle positive peak current limit iplimit (note 7) 1.3 1.5 1.7 a pfm peak current limit i pk_pfm 0.34 0.4 0.5 a zero cross threshold 15 ma negative current limit inlimit (note 7) -0.67 -0.6 -0.53 a power mosfet high-side r hds i phase = 100ma, v cc = 5v 250 350 m low-side r lds i phase = 100ma, v cc = 5v 90 130 m phase leakage current en = phase = 0v 300 na phase rise time t rise v in = 36v 10 ns en/sync input threshold falling edge, logic low 0.4 1v rising edge, logic high 1.2 1.4 v en logic input leakage current en = 0v/36v -0.5 0.5 a sync logic input leakage current sync = 0v 10 100 na sync = 5v 1.0 1.55 a notes: 6. test condition: v in = 36v, fb forced above regulation point (0.6v), no switch ing, and power mosfet gate charging current not included. 7. established by both current sense amplifier gain test and current sense amplifier output test @ i l = 0a. 8. parameters with min and/or max limits are 100% tested at +25 c, unless otherwise specified. te mperature limits established by characterization and are not production tested. 9. minimum on-time required to maintain loop stability. electrical specifications t a = -40c to +125c, v in = 3v to 36v, unless otherwise noted. typical values are at t a = +25c. boldface limits apply over the junction temperat ure range, -40c to +125c (continued) parameter symbol test conditions min (note 8) typ max (note 8) units
isl85410 8 fn8375.2 november 22, 2013 efficiency curves f sw = 500khz, t a = +25c figure 5. efficiency vs load, pfm, v out = 12v figure 6. efficiency vs load, pwm, v out = 12v figure 7. efficiency vs load, pfm, v out = 5v, l1 = 30h figure 8. efficiency vs load, pwm, v out = 5v, l1 = 30h figure 9. efficiency vs load, pfm, v out = 3.3v figure 10. efficiency vs load, pwm, v out = 3.3v 50 55 60 65 70 75 80 85 90 95 100 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 v in = 15v v in = 24v v in = 33v output load (a) efficiency (%) 50 55 60 65 70 75 80 85 90 95 100 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 v in = 15v v in = 24v v in = 33v output load (a) efficiency (%) 50 55 60 65 70 75 80 85 90 95 100 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 output load (a) efficiency (%) v in = 6v v in = 15v v in = 24v v in = 12v 50 55 60 65 70 75 80 85 90 95 100 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 output load (a) efficiency (%) v in = 6v v in = 15v v in = 24v v in = 12v 50 55 60 65 70 75 80 85 90 95 100 v in = 5v v in = 15v v in = 24v v in = 12v v in = 33v output load (a) efficiency (%) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 50 55 60 65 70 75 80 85 90 95 100 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 output load (a) efficiency (%) v in = 5v v in = 15v v in = 24v v in = 12v v in = 33v
isl85410 9 fn8375.2 november 22, 2013 figure 11. efficiency vs load, pfm, v out = 1.8v figure 12. efficiency vs load, pwm, v out = 1.8v figure 13. efficiency vs load, pwm, v out = 5v, l1 = 30h figure 14. v out regulation vs load, pfm, v out = 5v, l1 = 30h figure 15. v out regulation vs load, pwm, v out = 3.3v figure 16. v out regulation vs load, pfm, v out = 3.3v efficiency curves f sw = 500khz, t a = +25c (continued) 50 55 60 65 70 75 80 85 90 95 100 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 v in = 5v v in = 15v v in = 24v v in = 12v v in = 33v output load (a) efficiency (%) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 50 55 60 65 70 75 80 85 90 95 100 v in = 5v v in = 15v v in = 24v v in = 12v v in = 33v output load (a) efficiency (%) 4.993 4.994 4.995 4.996 4.997 4.998 4.999 5.000 5.001 5.002 5.003 5.004 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 output load (a) output voltage (v) v in = 6v v in = 15v v in = 24v v in = 12v 4.990 4.995 5.000 5.005 5.010 5.015 5.020 5.025 5.030 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 output load (a) output voltage (v) v in = 6v v in = 15v v in = 24v v in = 12v 3.316 3.317 3.318 3.319 3.320 3.321 3.322 3.323 3.324 3.325 3.326 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 output load (a) output voltage (v) v in = 5v v in = 15v v in = 12v v in = 33v v in = 24v 3.315 3.320 3.325 3.330 3.335 3.340 3.345 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 output load (a) output voltage (v) v in = 5v v in = 15v v in = 24v v in = 12v v in = 33v
isl85410 10 fn8375.2 november 22, 2013 figure 17. v out regulation vs load, pwm, v out = 1.8v figure 18. v out regulation vs load, pfm, v out = 1.8v efficiency curves f sw = 500khz, t a = +25c (continued) 1.800 1.801 1.802 1.803 1.804 1.805 1.806 1.807 1.808 1.809 1.810 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 v in = 5v v in = 15v v in = 24v v in = 33v v in = 12v output load (a) output voltage (v) 1.800 1.802 1.804 1.806 1.808 1.810 1.812 1.814 1.816 1.818 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 output load (a) output voltage (v) v in = 5v v in = 15v v in = 24v v in = 33v v in = 12v measurements f sw = 500khz, v in = 24v, v out = 3.3v, t a = +25c figure 19. start-up at no load, pfm f igure 20. start-up at no load, pwm figure 21. shutdown at no load, pfm figure 22. shutdown at no load, pwm lx 20v/div v out 2v/div en 20v/div pg 2v/div 5ms/div lx 20v/div v out 2v/div en 20v/div pg 2v/div 5ms/div lx 20v/div v out 2v/div en 20v/div pg 2v/div 100ms/div lx 20v/div v out 2v/div en 20v/div pg 2v/div 100ms/div
isl85410 11 fn8375.2 november 22, 2013 figure 23. start-up at 1a, pwm figure 24. shutdown at 1a, pwm figure 25. start-up at 1a, pfm figure 26. shutdown at 1a, pfm figure 27. jitter at no load, pw m figure 28. jitter at 1a load, pwm measurements f sw = 500khz, v in = 24v, v out = 3.3v, t a = +25c (continued) lx 20v/div v out 2v/div i l 500ma/div pg 2v/div 5ms/div lx 20v/div v out 2v/div i l 500ma/div pg 2v/div 200s/div lx 20v/div v out 2v/div i l 500ma/div pg 2v/div 5ms/div lx 20v/div v out 2v/div i l 500ma/div pg 2v/div 200s/div lx 5v/div 5ns/div lx 5v/div 5ns/div
isl85410 12 fn8375.2 november 22, 2013 figure 29. steady state at no load, pfm figure 30. steady state at no load, pwm figure 31. steady state at 1a, pwm figure 32. light load operation at 20ma, pfm figure 33. light load operation at 20ma, pwm figure 34. load transient, pfm measurements f sw = 500khz, v in = 24v, v out = 3.3v, t a = +25c (continued) lx 20v/div v out 20mv/div i l 20ma/div 10ms/div lx 20v/div v out 20mv/div i l 20ma/div 1s/div lx 20v/div i l 1a/div 1s/div v out 20mv/div lx 20v/div i l 200ma/div 10s/div v out 50mv/div lx 20v/div i l 200ma/div 1s/div v out 10mv/div i l 1a/div 200s/div v out 100mv/div
isl85410 13 fn8375.2 november 22, 2013 figure 35. load transient, pwm figure 36. pfm to pwm transition figure 37. overcurrent protection, pwm figure 38. overcurrent protection hiccup, pwm figure 39. sync at 1a load, pwm figure 40. negative current limit, pwm measurements f sw = 500khz, v in = 24v, v out = 3.3v, t a = +25c (continued) i l 1a/div 200s/div v out 100mv/div lx 20v/div i l 1a/div v out 20mv/div 10s/div lx 20v/div v out 2v/div i l 1a/div pg 2v/div 50s/div lx 20v/div v out 2v/div i l 1a/div pg 2v/div 10ms/div lx 20v/div sync 2v/div 200ns/div lx 20v/div v out 5v/div i l 1a/div pg 2v/div 20s/div
isl85410 14 fn8375.2 november 22, 2013 detailed description the isl85410 combines a sync hronous buck pwm controller with integrated power switches. the buck controller drives internal high-side and low-side n-channel mosfets to deliver load current up to 1a. the buck regulator can operate from an unregulated dc source, such as a battery, with a voltage ranging from +3v to +36v. an internal ldo provides bias to the low voltage portions of the ic. peak current mode control is utilized to simplify feedback loop compensation and reject input volt age variation. user selectable internal feedback loop compensa tion further simplifies design. the isl85410 switches at a default 500khz. the buck regulator is equipped with an internal current sensing circuit and the peak current limi t threshold is typically set at 0.9a. power-on reset the isl85410 automatically initia lizes upon receipt of the input power supply and continually monitors the en pin state. if en is held below its logic rising thresh old the ic is held in shutdown and consumes typically 1a from the vin supply. if en exceeds its logic rising threshold, the regulator will enable the bias ldo and begin to monitor the vcc pin voltage. when the vcc pin voltage clears its rising por threshold the controller will initialize the switching regulator circuits. if vcc never clears the rising por threshold, the controller will no t allow the switching regulator to operate. if vcc falls below its falling por threshold while the switching regulator is operating, the switching regulator will be shut down until vcc returns. soft start to avoid large in-rush current, v out is slowly increased at startup to its final regulated value. soft-start time is determined by the ss pin connection. if ss is pulled to vcc, an internal 2ms timer is selected for soft-start. for other soft-start times, simply connect a capacitor from ss to gnd. in this case, a 5.5a current pulls up the ss voltage and the fb pin will follow this ramp until it reaches the 600mv reference level. soft-start time for this case is described by equation 1: power-good pg is the open-drain output of a window comparator that continuously monitors the buck regulator output voltage via the fb pin. pg is actively held low when en is low and during the buck regulator soft-start period. after the soft-start period completes, pg becomes high impedance provided the fb pin is within the range specified in th e ?electrical specifications? on page 3. should fb exit the specified window, pg will be pulled low until fb returns. over-temperature faults also force pg low until the fault condition is cleare d by an attempt to soft-start. there is an internal 5m internal pull-up resistor. pwm control scheme the isl85410 employs peak current-mode pulse-width modulation (pwm) control for fast transient response and pulse-by-pulse current limiting, as shown in the ?functional block diagram? on page 5. the current loop consists of the current sensing circuit, slope compensation ramp, pwm comparator, oscillator and latch. current sens e trans-resistance is typically 600mv/a and slope compensation rate, se, is typically 450mv/t where t is the switching cycle period. the control reference for the current loop comes from the error amplifier?s output (v comp ). a pwm cycle begins when a clock pulse sets the pwm latch and the upper fet is turned on. current begins to ramp up in the upper fet and inductor. this current is sensed (v csa ), converted to a voltage and summed with the slope compen sation signal. this combined signal is compared to v comp and when the signal is equal to v comp , the latch is reset. upon latch reset the upper fet is turned off and the lower fet turned on allowing current to ramp down in the inductor. the lower fet will rema in on until the clock initiates another pwm cycle. figure 44 shows the typical operating waveforms during the pwm operation. the dotted lines illustrate the sum of the current sense and slope compensation signal. output voltage is regulated as the error amplifier varies vcomp and thus output inductor curr ent. the error amplifier is a trans-conductance type and its outp ut (comp) is terminated with a series rc network to gnd. this termination is internal (150k/54pf) if the comp pin is tied to vcc. additionally, the trans-conductance for comp = vcc is 50s vs 220s for external rc connection. its non-inverting input is internally connected to a 600mv reference voltage and its inverting input is connected to the output voltage via the fb pin and its associated divider network. figure 41. negative current limit recovery, pwm figure 42. over-temper ature protection, pwm measurements f sw = 500khz, v in = 24v, v out = 3.3v, t a = +25c (continued) lx 20v/div v out 5v/div i l 500ma/div pg 2v/div 200s/div v out 2v/div pg 2v/div 500s/div time ms () cnf () ? 0.109 = (eq. 1)
isl85410 15 fn8375.2 november 22, 2013 light load operation at light loads, converter efficiency may be improved by enabling variable frequency operation (pfm ). connecting the sync pin to gnd will allow the controller to choose such operation automatically when the load current is low. figure 43 shows the dcm operation. the ic enters the dcm mode of operation when 8 consecutive cycles of inductor current crossing zero are detected. this corresponds to a load current equal to 1/2 the peak-to-peak inductor ripple current and set by the following equation 2: where d = duty cycle, f s = switching frequency, l = inductor value, i out = output loading current, v out = output voltage. while operating in pfm mode, the regulator controls the output voltage with a simple comparat or and pulsed fet current. a comparator signals the point at which fb is equal to the 600mv reference at which time the regulator begins providing pulses of current until fb is moved above the 600mv reference by 1%. the current pulses are approximatel y 300ma and are issued at a frequency equal to the converters programmed pwm operating frequency. due to the pulsed current nature of pfm mode, the converter can supply limited current to the load. should load current rise beyond the limit, vout will begin to decline. a second comparator signals an fb voltage 1% lower than the 600mv reference and forces the converter to return to pwm operation. output voltage selection the regulator output voltage is easily programmed using an external resistor divider to scale v out relative to the internal reference voltage. the scaled voltage is applied to the inverting input of the error amplifier; refer to figure 43. the output voltage programming resistor, r 3 , depends on the value chosen for the feedback resistor, r 2 , and the desired output voltage, v out , of the regulator. equation 3 describes the relationship between v out and resistor values. if the desired output voltage is 0.6v, then r 3 is left unpopulated and r 2 is 0 ? . protection features the isl85410 is protected from overcurrent, negative overcurrent and over-temperature. the protection circuits operate automatically. overcurrent protection during pwm on-time, current through the upper fet is monitored and compared to a nominal 0.9a peak overcurrent limit. in the event that current reaches the limi t, the upper fet will be turned off until the next switching cycle. in this way, fet peak current is always well limited. figure 43. dcm mode operation waveforms clock i l v out 0 8 cycles pwm dcm pwm load current pulse skip dcm figure 44. pwm operation waveforms v comp v csa duty cycle i l v out i out v out 1d ? () 2lf s ---------------------------------- - = (eq. 2) r 3 r 2 x0.6v v out 0.6v ? ---------------------------------- = (eq. 3) r 2 r 3 0.6v ea reference + - v out figure 45. external resistor divider fb
isl85410 16 fn8375.2 november 22, 2013 if the overcurrent condition pers ists for 17 sequential clock cycles, the regulator will begin its hiccup sequence. in this case, both fets will be turned off and pg will be pulled low. this condition will be maintained for 8 soft-start periods after which, the regulator will attempt a normal soft-start. should the output fault persist, the regulator will repeat the hiccup sequence indefinitely. th ere is no danger even if the output is shorted during soft-start. if v out is shorted very quickly, fb may collapse below 5/8 ths of its target value before 17 cycles of overcurrent are detected. the isl85410 recognizes this condition and will begin to lower its switching frequency proportional to the fb pin voltage. this insures that under no circumstance (even with v out near 0v) will the inductor current run away. negative current limit should an external source somehow drive current into v out , the controller will attempt to regulate v out by reversing its inductor current to absorb the externally so urced current. in the event that the external source is low impeda nce, current may be reversed to unacceptable levels and the cont roller will initiate its negative current limit protection. simila r to normal overcurrent, the negative current protection is re alized by monitoring the current through the lower fet. when th e valley point of the inductor current reaches negative current lim it, the lower fet is turned off and the upper fet is forced on until current reaches the positive current limit or an internal clock si gnal is issued. at this point, the lower fet is allowed to operate. should the current again be pulled to the negative limit on the next cycle, the upper fet will again be forced on and current will be forced to 1/6 th of the positive current limit. at this point the controller wi ll turn off both fet?s and wait for comp to indicate return to normal operation. during this time, the controller will apply a 100 load from phase to pgnd and attempt to discharge the output . negative current limit is a pulse-by-pulse style operation and recovery is automatic. over-temperature protection over-temperature protection limits maximum junction temperature in the isl85410. when junction temperature (t j ) exceeds +150c, both fet?s are turned off and the controller waits for temperature to decrease by approximately 20c. during this time pg is pulled low. when temperature is within an acceptable range, the controller w ill initiate a normal soft-start sequence. for continuous operation, the +125c junction temperature rating should not be exceeded. boot undervoltage protection if the boot capacitor voltage falls below 1.8v, the boot undervoltage protection circuit will turn on the lower fet for 400ns to recharge the capacitor. this operation may arise during long periods of no switching such as pfm no load situations. in pwm operation near dropout (v in near v out ), the regulator may hold the upper fet on for multiple clock cycles. to prevent the boot capacitor from discharging, the lower fet is forced on for approximately 200ns every 10 clock cycles. application guidelines simplifying the design while the isl85410 offers user programmed options for most parameters, the easiest implementation with fewest components involves selecting internal settings for ss, comp and fs. table 1 on page 4 provides component value selections for a variety of output voltages and will allow the designer to implement solutions with a minimum of effort. operating frequency the isl85410 operates at a default switching frequency of 500khz if f s is tied to v cc . tie a resistor from f s to gnd to program the switching frequenc y from 300khz to 2mhz, as shown in equation 4. where: t is the switching period in s. synchronization control the frequency of operation can be synchronized up to 2mhz by an external signal applied to the sync pin. the rising edge on the sync triggers the rising edge of phase. to properly sync, the external source must be at least 10% greater than the programmed free ru nning ic frequency. output inductor selection the inductor value determines the converter?s ripple current. choosing an inductor current re quires a somewhat arbitrary choice of ripple current, i . a reasonable starting point is 30% of total load current. the inductor value can then be calculated using equation 5: increasing the value of inductance reduces the ripple current and thus, the ripple voltage. however, the larger inductance value may reduce the converter?s respon se time to a load transient. the inductor current rating should be such that it will not saturate r fs k [] 108.75k ? t ( 0.2 s ) 1 s ? ? = (eq. 4) figure 46. r fs selection vs f s 300 200 100 0 500 750 1000 1250 1500 1750 2000 fs (khz) r fs (k ? ) l= v in - v out fs x di v out v in x (eq. 5)
isl85410 17 fn8375.2 november 22, 2013 in overcurrent conditions. for typical isl85410 applications, inductor values generally lies in the 10h to 47h range. in general, higher v out will mean higher inductance. buck regulator output capacitor selection an output capacitor is required to filter the inductor current. the current mode control loop allows the use of low esr ceramic capacitors and thus supports ve ry small circuit implementations on the pc board. electrolytic and polymer capacitors may also be used. while ceramic capacitors offer excellent overall performance and reliability, the actual in-circuit capacitance must be considered. ceramic capacitors are rated using large peak-to-peak voltage swings and with no dc bias. in the dc/dc converter application, these conditio ns do not reflect reality. as a result, the actual capacitance ma y be considerably lower than the advertised value. consult the manufacturers data sheet to determine the actual in-application capacitance. most manufacturers publish capacitance vs dc bias so that this effect can be easily accommodated. the effects of ac voltage are not frequently published, but an assumption of ~20% further reduction will generally suffice. the result of these considerations may mean an ef fective capacitance 50% lower than nominal and this value should be used in all design calculations. nonetheless, ceramic capacitors are a very good choice in many applications due to their reliability and extremely low esr. the following equations allow calculation of the required capacitance to meet a desired ripple voltage level. additional capacitance may be used. for the ceramic capacitors (low esr): where i is the inductor?s peak-to-peak ripple current, f sw is the switching frequency and c out is the output capacitor. if using electrolytic capacitors then: loop compensation design when comp is not connected to vcc, the comp pin is active for external loop compensation. the isl85410 uses constant frequency peak current mode control architecture to achieve a fast loop transient response. an accurate current sensing pilot device in parallel with the upper mosfet is used for peak current control signal and overcurrent protection. the inductor is not considered as a state variable si nce its peak current is constant, and the system becomes a single or der system. it is much easier to design a type ii compensator to stabilize the loop than to implement voltage mode control. peak current mode control has an inherent input voltage feed-forward function to achieve good line regulation. figure 47 show s the small signal model of the synchronous buck regulator. figure 48 shows the type ii compensator and its transfer function is expressed, as shown in equation 8: where , compensator design goal: high dc gain choose loop bandwidth f c less than 100khz gain margin: >10db phase margin: >40 the compensator design procedure is as follows: the loop gain at crossover frequency of f c has a unity gain. therefore, the compensator resistance r 6 is determined by v outripple i 8 ? f sw ? c out -------------------------------------- - = (eq. 6) v outripple i*esr = (eq. 7) d v in d i l in in i l + 1:d + l i co rc -av(s) d comp v r t fm he(s) + t i (s) k o v t v (s) i l p + 1:d + rc ro -av(s) r t fm he(s) t i (s) k o t(s) ^ ^ v ^ ^ ^ ^ ^ ^ figure 47. small signal model of synchronous buck regulator r lp gain (vloop (s(fi)) - + r6 v v vo gm v c7 - + c6 v ref v fb vo v comp figure 48. type ii compensator c3 r2 r3 a v s () v ? comp v ? fb ------------------- - gm r 3 ? c 6 c 7 + () r 2 r 3 + () ? -------------------------------------------------------- 1 s cz1 ------------ - + ?? ?? 1 s cz2 ------------ - + ?? ?? s1 s cp1 ------------- + ?? ?? 1 s cp2 ------------- + ?? ?? -------------------------------------------------------------- - = = (eq. 8) cz1 1 r 6 c 6 -------------- - cz2 1 r 2 c 3 -------------- - = cp1 , c 6 c 7 + r 6 c 6 c 7 ---------------------- - cp2 r 2 r 3 + c 3 r 2 r 3 ---------------------- - = , = , =
isl85410 18 fn8375.2 november 22, 2013 equation 9. where gm is the trans-conductance, g m , of the voltage error amplifier in each phase. compensator capacitor c 6 is then given by equation 10. put one compensator pole at zero frequency to achieve high dc gain, and put another compensator pole at either esr zero frequency or half switching frequency, whichever is lower in equation 10. an optional zero can boost the phase margin. cz2 is a zero due to r 2 and c 3 . put compensator zero 2 to 5 times f c example: v in = 12v, v o = 5v, i o = 1a, fs = 500khz, r 2 = 90.9k , c o = 22f/5m ? , l = 39h, f c = 50khz, then compensator resistance r 6 : it is acceptable to use 124k as the closest standard value for r 6 . it is also acceptable to use th e closest standard values for c 6 and c 7 . there is approximately 3pf parasitic capacitance from v comp to gnd; therefore, c 7 is optional. use c 6 = 1500pf and c 7 = open. use c 3 = 68pf. note that c 3 may increase the loop bandwidth from previous estimated value. figure 49 shows the simulated voltage loop gain. it is shown that it has a 75khz loop bandwidth with a 61 phase margin and 6db gain margin. it may be more desirable to achieve an increased gain margin. this can be accomplished by lowering r 6 by 20% to 30%. in practice, ceramic capacitors have significant derating on voltage and temperature, depending on the type. please refer to the ceramic capacitor datasheet for more details. layout considerations proper layout of the power converter will minimize emi and noise and insure first pass success of the design. pcb layouts are provided in multiple formats on the intersil web site. in addition, figure 50 will make clear the important points in pcb layout. in reality, pcb layout of the isl85410 is quite simple. a multi-layer printed circuit board with gnd plane is recommended. figure 50 shows the connections of the critical components in the converter. note that capacitors c in and c out could each represent multiple physical capacitors. the most critical connections are to tie the pgnd pin to the package gnd pad and then use vias to directly connect the gnd pad to the system gnd plane. this connection of the gnd pad to system plane insures a low impedance path for all return current, as well as an excellent thermal path to dissipate heat. with this connection made, place the high frequency mlcc input capacitor near the vin pin and use vias directly at the capacitor pad to tie the capacitor to the system gnd plane. the boot capacitor is easily placed on the pcb side opposite the controller ic and 2 vias directly connect the capacitor to boot and phase. place a 1f mlcc near the vcc pin and directly connect its return with a via to the system gnd plane. place the feedback divider close to the fb pin and do not route any feedback components near phase or boot. if external components are used for ss, comp or fs the same advice applies. r 6 2 f c v o c o r t gm v fb ? --------------------------------- - 22.75 3 10 f c v o c o ? == (eq. 9) c 6 r o c o r 6 -------------- - v o c o i o r 6 -------------- - c 7 max r c c o r 6 -------------- - 1 f s r 6 --------------- - (, ) = , = = (eq. 10) c 3 1 f c r 2 --------------- - = (eq. 11) r 6 22.75 3 10 50khz 5v 22 f ? ? ? 125.12k == (eq. 12) c 6 5v 22 ? f 1a 124k ? ------------------------------ 0.88nf = = (eq. 13) c 7 max 5m 22 f ? 124k -------------------------------- - 1 500khz 124k ?? ---------------------------------------------------- (, ) 0.88pf 5.1pf (,) = = (eq. 14) c 3 1 50khz 90.9k ?? -------------------------------------------------- = 70pf = (eq. 15) figure 49. simulated loop gain 60 45 30 15 0 -15 -30 100 1k 10k 100k 1m frequency (hz) 180 150 120 90 60 30 0 100 1k 10k 100k 1m frequency (hz) phase ( ) gain (db)
isl85410 19 fn8375.2 november 22, 2013 l1 cout cvin css rfs cvcc figure 50. printed circuit boar d power planes and islands
isl85410 20 intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn8375.2 november 22, 2013 for additional products, see www.intersil.com/en/products.html about intersil intersil corporation is a leader in the design and manufacture of high-performance analog, mixed-signal and power management semiconductors. the company's products addr ess some of the largest markets within th e industrial and infr astructure, personal computing and high-end consumer markets. for more information about intersil, visit our website at www.intersil.com . for the most updated datasheet, application notes, related documentatio n and related parts, please see the respective product information page found at www.intersil.com . you may report errors or suggestions fo r improving this datasheet by visiting www.intersil.com/en/support/ask-an-expert.html . reliability reports are also available from our website at http://www.intersil.com/en/support/q ualandreliability.html#reliability revision history the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest revision. date revision change november 22, 2013 fn8375.2 initial release.
isl85410 21 fn8375.2 november 22, 2013 package outline drawing l12.4x3 12 lead dual flat no-lead plastic package rev 2, 7/10 1.70 +0.10/-0.15 12 x 0.40 0.10 12 0.10 12 x 0.23 +0.07/-0.05 4 7 ab c m pin #1 index area 6 1 2x 2.50 6 10x 0.50 3.30 +0.10/-0.15 typical recommended land pattern detail "x" top view bottom view side view located within the zone indicated. the pin #1 identifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 identifier is optional, but must be between 0.15mm and 0.30mm from the terminal tip. dimension applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: (4x) 0.15 3.00 index area 6 pin 1 4.00 b a 1.00 max see detail "x" c seating plane 0.08 c 0.10 c ( 3.30) 2.80 ( 10x 0 . 5 ) ( 12x 0.23 ) ( 1.70 ) 12 x 0.60 0.2 ref c 0 . 05 max. 0 . 00 min. 5 compliant to jedec mo-229 v4030d-4 issue e. 7. 1 6 712

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